Special Reports

Designing Electro-Optical Chips

By: Ann Mutschler

Photonics is forcing EDA to verify not just chips, but the physics of light inside full electro-optical systems.
When The Test Cell Lies

By: Gregory Haley

As margins shrink and dies move into expensive packages, separating device failures from test-cell artifacts has become a first-order economic...
Rethinking Chip Verification

By: Ann Mutschler

Specification engineering is gaining traction as a potential solution to the verification bottleneck.

 more »

Top Stories

Self-Driving Cars Have An Aging Problem

AI workloads are pushing automotive sensors harder, forcing engineers to rethink how lo...

Compute Clusters Break Out Of National Labs To Scale AI

For compute-intensive applications, clusters of nodes that act as a single computer off...

Flat Enough? Warpage Management Gets Harder In Advanced Packaging

As packages get larger and thinner, warpage is becoming a process-control problem rathe...

Preparing For AI-Driven Chip Design And Verification

Jobs, markets, and economics are undergoing dramatic changes, but it's still too early ...

Untangling Chip Traffic Jams

Scaling NoCs across chiplets requires earlier validation of coherency, congestion, ther...

The Impact Of AI Automation On Chip Design

Change is coming, but how quickly depends on the availability of data and when chipmake...

From Highways To Health Care: Portability Proves Key To Physical AI

Success at the edge takes advantage of common threads — lithography, imaging, chiplet...

Data Center Chokepoints Tied To AI, Political Pressure, Supply Chain

Technical, political, and supply chain challenges are complicating data center buildout...

Can Fine-Pitch Hybrid Bonding Go High Volume?

Hybrid bonding already works in production, but finer-pitch die-to-wafer integration mu...

New Nonvolatile Memory Winners Emerge

RRAM, MRAM have promising futures, while FeRAM lurks, and UltraRAM plans a debut.

Alternative Materials For Hybrid Bonding

Nanotwinned copper, SiCN, BCB, and passivating metals are all possibilities

AI In Chip Design: Lots Of Promise, Plenty Of Unanswered Questions

Where AI will be successful, who will benefit, and how that will affect the design proc...

Startup Funding: Q2 2026

Plenty of cash for AI and its enablers; 80 startups raise over $6B.

AI Is Rewriting The IP Playbook

As the semiconductor ecosystem pivots to AI, it is transforming how IP is created, veri...

Where Does Quantum Computing Stand?

It's slowly emerging from research and heading toward high-volume production.

An AI Model Fit For Purpose

Using models outside the context in which they were created for can result in misleadin...

Multi-die Testing In The Field Must Build On Established Test Methodologies

Having a device that works at time zero is no longer a guarantee of reliability over it...

Inspection And Metrology Catching Up For High-Density Fan-Out Panel Packaging

Optical methods need to comply with increasing warpage, finer RDL pitch, and trace size.

AI Data Centers And Auto Industry Converge On Same Issues

The EV revolution relies on battery innovation, while AI data centers need a range of n...

Defending Against AI-Enabled Data Fusion

As multimodal AI fuses data from billions of devices, attackers can weaponize detailed ...

more top stories »

Latest News

Chip Industry Week In Review

DAC's big buzz; CHIPS Act $; China's immersion DUV; UMC expands; SIA's state of the industry; DRAM shortages; earnings; PCB design credential program; IBM's quant...

Blog Review: July 29

Rethinking AI compute; DFI 6; 3D-IC reliability; local AI in browser; surface prep and cleaning.

Chip Industry Week In Review

Amkor's $1.5B deal; Intel Foundry revenue up 31%; Siemens' dual buys; SiC plant dies; AMD's big week; TSMC price hike; Nokia's fab buy; earnings; $300M for accele...

more news »



Opinion

Why the Semiconductor Industry Needs A Common Language For Functional Safety

A standardized way for future automation.

Change Is Tough

There has never been a time when change has become something e...

more opinions »



Research

Chip Industry Technical Paper Roundup: July 28

HW methods to throttle AI; M3D DRAM; interconnect signal-integ...

Research Bits: July 28

Photonics: Inverse design; slowing down light; on-chip electro...

Chip Industry Technical Paper Roundup: July 21

Near-memory HBM for LLM inference; processing-in-memory for 3D...

more research »



Startup Corner

Startup Funding: Q2 2026

Plenty of cash for AI and its enablers; 80 startups raise over...

Startup Funding: Q1 2026

Massive rounds for AI, EDA, and manufacturing; 80 startups rai...

more startups »

Videos

AI Agent Orchestration For ASIC Autonomy


Verifying Networks On Chip


AI Models On The Edge


How Far Left Can You Shift?


Knowledge Centers / Entities, people and technologies explored